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ltc2228/ltc2227/ltc2226 1 222876fb typical application features applications description 12-bit, 65/40/25msps low power 3v adcs the ltc ? 2228/ltc2227/ltc2226 are 12-bit 65msps/ 40msps/25msps, low power 3v a/d converters designed for digitizing high frequency, wide dynamic range signals. the ltc2228/ltc2227/ltc2226 are perfect for demand- ing imaging and communications applications with ac performance that includes 71.3db snr and 90db sfdr for signals at the nyquist frequency. dc specs include 0.3lsb inl (typ), 0.15lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 0.25lsb rms . a single 3v supply allows low power operation. a separate output supply allows the outputs to drive 0.5v to 3.6v logic. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. ltc2228: snr vs input frequency, C1db, 2v range, 65msps n sample rate: 65msps/40msps/25msps n single 3v supply (2.7v to 3.4v) n low power: 205mw/120mw/75mw n 71.3db snr n 90db sfdr n no missing codes n flexible input: 1v p-p to 2v p-p range n 575mhz full power bandwidth s/h n clock duty cycle stabilizer n shutdown and nap modes n pin compatible family 125msps: ltc2253 (12-bit), ltc2255 (14-bit) 105msps: ltc2252 (12-bit), ltc2254 (14-bit) 80msps: ltc2229 (12-bit), ltc2249 (14-bit) 65msps: ltc2228 (12-bit), ltc2248 (14-bit) 40msps: ltc2227 (12-bit), ltc2247 (14-bit) 25msps: ltc2226 (12-bit), ltc2246 (14-bit) 10msps: ltc2225 (12-bit), ltc2245 (14-bit) n 32-pin (5mm 5mm) qfn package n wireless and wired broadband communication n imaging systems n ultrasound n spectral analysis n portable instrumentation l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. C + input s/h correction logic output drivers 12-bit pipelined adc core clock/duty cycle control flexible reference d11 ?? ? d0 clk refh refl analog input 222876 ta01 ov dd ognd input frequency (mhz) 0 snr (dbfs) 70 71 200 2228 g09 6968 50 100 150 72 downloaded from: http:///
ltc2228/ltc2227/ltc2226 2 222876fb pin configuration absolute maximum ratings supply voltage (v dd ) ..................................................4v digital output ground voltage (ognd) ........ C0.3v to 1v analog input voltage (note 3) .......C0.3v to (v dd + 0.3v) digital input voltage ......................C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) power dissipation .............................................1500mw operating temperature range ltc2228c, ltc2227c, ltc2226c............. 0c to 70c ltc2228i, ltc2227i, ltc2226i ............ C40c to 85c storage temperature range ................... C65c to 125c ov dd = v dd (notes 1, 2) 32 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm s 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 a in + a in C refhrefh reflrefl v dd gnd d8d7 d6 ov dd ogndd5 d4 d3 v dd v cm sensemode of d11 d10 d9 clk shdn oe ncnc d0d1 d2 33 t jmax = 125c, ja = 34c/w exposed pad (pin 33) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc2228cuh#pbf ltc2228cuh#trpbf 2228 32-lead (5mm 5mm) plastic qfn 0c to 70c ltc2228iuh#pbf ltc2228iuh#trpbf 2228 32-lead (5mm 5mm) plastic qfn C40c to 85c ltc2227cuh#pbf ltc2227cuh#trpbf 2227 32-lead (5mm 5mm) plastic qfn 0c to 70c ltc2227iuh#pbf ltc2227iuh#trpbf 2227 32-lead (5mm 5mm) plastic qfn C40c to 85c LTC2226CUH#pbf LTC2226CUH#trpbf 2226 32-lead (5mm 5mm) plastic qfn 0c to 70c ltc2226iuh#pbf ltc2226iuh#trpbf 2226 32-lead (5mm 5mm) plastic qfn C40c to 85c lead based finish tape and reel part marking* package description temperature range ltc2228cuh ltc2228cuh#tr 2228 32-lead (5mm 5mm) plastic qfn 0c to 70c ltc2228iuh ltc2228iuh#tr 2228 32-lead (5mm 5mm) plastic qfn C40c to 85c ltc2227cuh ltc2227cuh#tr 2227 32-lead (5mm 5mm) plastic qfn 0c to 70c ltc2227iuh ltc2227iuh#tr 2227 32-lead (5mm 5mm) plastic qfn C40c to 85c LTC2226CUH LTC2226CUH#tr 2226 32-lead (5mm 5mm) plastic qfn 0c to 70c ltc2226iuh ltc2226iuh#tr 2226 32-lead (5mm 5mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc2228/ltc2227/ltc2226 3 222876fb converter characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) parameter conditions ltc2228 ltc2227 ltc2226 units min typ max min typ max min typ max resolution (no missing codes) l 12 12 12 bits integral linearity error differential analog input (note 5) l C1.1 0.3 1.1 C1 0.3 1 C1 0.3 1 lsb differential linearity error differential analog input l C0.8 0.15 0.8 C0.7 0.15 0.7 C0.7 0.15 0.7 lsb offset error (note 6) l C12 2 12 C12 2 12 C12 2 12 mv gain error external reference l C2.5 0.5 2.5 C2.5 0.5 2.5 C2.5 0.5 2.5 %fs offset drift 10 10 10 v/c full-scale drift internal reference 30 30 30 ppm/c external reference 5 5 5 ppm/c transition noise sense = 1v 0.25 0.25 0.25 lsb rms analog input the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 2.7v < v dd < 3.4v (note 7) l 0.5v to 1v v v in,cm analog input common mode (a in + + a in C )/2 differential input (note 7) single-ended input (note 7) ll 1 0.5 1.51.5 1.9 2 vv i in analog input leakage current 0v < a in + , a in C < v dd l C1 1 a i sense sense input leakage 0v < sense < 1v l C3 3 a i mode mode pin leakage l C3 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms cmrr analog input common mode rejection ratio 80 db full power bandwidth figure 8 test circuit 575 mhz dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4) symbol parameter conditions ltc2228 ltc2227 ltc2226 units min typ max min typ max min typ max snr signal-to-noise ratio 5mhz input 71.3 71.4 71.4 db 12.5mhz input l 70.2 71.2 db 20mhz input l 70.1 71.3 db 30mhz input l 70 71.3 db 70mhz input 71.3 71.1 70.9 db 140mhz input 71 70.7 70.6 db sfdr spurious free dynamic range 2nd or 3rd harmonic 5mhz input 90 90 90 db 12.5mhz input l 76 90 db 20mhz input l 76 90 db 30mhz input l 75 90 db 70mhz input 85 85 85 db 140mhz input 80 80 80 db downloaded from: http:///
ltc2228/ltc2227/ltc2226 4 222876fb dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4) symbol parameter conditions ltc2228 ltc2227 ltc2226 units min typ max min typ max min typ max sfdr spurious free dynamic range4th harmonic or higher 5mhz input 95 95 95 db 12.5mhz input l 82 95 db 20mhz input l 82 95 db 30mhz input l 82 95 db 70mhz input 95 95 95 db 140mhz input 90 90 90 db s/(n+d) signal-to-noise plus distortionratio 5mhz input 71.3 71.4 71.4 db 12.5mhz input l 69.8 71.2 db 20mhz input l 69.7 71.2 db 30mhz input l 69.6 71.2 db 70mhz input 71.1 70.9 70.8 db 140mhz input 69.9 69.9 69.8 db imd intermodulation distortion f in1 = 28.2mhz, f in2 = 26.8mhz 90 90 90 db parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.500 1.525 v v cm output tempco 25 ppm/c v cm line regulation 2.7v < v dd < 3.4v 3 mv/v v cm output resistance C1ma < i out < 1ma 4 internal reference characteristics (note 4) digital inputs and digital outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units logic inputs (clk, oe , shdn) v ih high level input voltage v dd = 3v l 2v v il low level input voltage v dd = 3v l 0.8 v i in input current v in = 0v to v dd l C10 10 a c in input capacitance (note 7) 3 pf logic outputsov dd = 3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = C10a i o = C200a l 2.7 2.995 2.99 vv v ol low level output voltage i o = 10a i o = 1.6ma l 0.005 0.09 0.4 vv ov dd = 2.5v v oh high level output voltage i o = C200a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = C200a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v downloaded from: http:///
ltc2228/ltc2227/ltc2226 5 222876fb power requirements the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 8) symbol parameter conditions ltc2228 ltc2227 ltc2226 units min typ max min typ max min typ max v dd analog supply voltage (note 9) l 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 v ov dd output supply voltage (note 9) l 0.5 3 3.6 0.5 3 3.6 0.5 3 3.6 v i vdd supply current l 68.3 80 40 48 25 30 ma p diss power dissipation l 205 240 120 144 75 90 mw p shdn shutdown power shdn = h, oe = h, no clk 222 m w p nap nap mode power shdn = h, oe = l, no clk 15 15 15 mw timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions ltc2228 ltc2227 ltc2226 units min typ max min typ max min typ max f s sampling frequency (note 9) l 1 65 1 40 1 25 mhz t l clk low time duty cycle stabilizer off duty cycle stabilizer on (note 7) ll 7.3 5 7.77.7 500500 11.8 5 12.5 500 500 18.9 5 2020 500500 nsns t h clk high time duty cycle stabilizer off duty cycle stabilizer on (note 7) ll 7.3 5 7.77.7 500500 11.8 5 12.512.5 500500 18.9 5 2020 500500 nsns t ap sample-and-hold aperture delay 000 n s t d clk to data delay c l = 5pf (note 7) l 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns data access time after oe c l = 5pf (note 7) l 4.3 10 4.3 10 4.3 10 ns bus relinquish time (note 7) l 3.3 8.5 3.3 8.5 3.3 8.5 ns pipeline latency 5 5 5 cycles note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3v, f sample = 65mhz (ltc2228), 40mhz (ltc2227), or 25mhz (ltc2226), input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C0.5 lsb when the output code ? ickers between 0000 0000 0000 and 1111 1111 1111. note 7: guaranteed by design, not subject to test. note 8: v dd = 3v, f sample = 65mhz (ltc2228), 40mhz (ltc2227), or 25mhz (ltc2226), input range = 1v p-p with differential drive. note 9: recommend operating conditions. downloaded from: http:///
ltc2228/ltc2227/ltc2226 6 222876fb typical performance characteristics ltc2228: typical inl, 2v range, 65msps ltc2228: typical dnl, 2v range, 65msps ltc2228: 8192 point fft, f in = 5mhz, C1db, 2v range, 65msps ltc2228: 8192 point fft, f in = 30mhz, C1db, 2v range, 65msps ltc2228: 8192 point 2-tone fft, f in = 28.2mhz and 26.8mhz, C1db, 2v range, 65msps ltc2228: grounded input histogram, 65msps ltc2228: snr vs input frequency, C1db, 2v range, 65msps code 0 inl error (lsb) 3072 2228 g01 1024 2048 4096 1.000.75 0.50 0.25 0 C0.25C0.50 C0.75 C1.00 code 0 dnl error (lsb) 3072 2228 g02 1024 2048 4096 1.000.75 0.50 0.25 0 C0.25C0.50 C0.75 C1.00 frequency (mhz) 0 2228 g03 51015 amplitude (db) 20 25 30 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100C110 C120 ltc2228: 8192 point fft, f in = 70mhz, C1db, 2v range, 65msps ltc2228: 8192 point fft, f in = 140mhz, C1db, 2v range, 65msps frequency (mhz) 0 2228 g04 51015 amplitude (db) 20 25 30 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100C110 C120 frequency (mhz) 0 2228 g05 51015 amplitude (db) 20 25 30 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100C110 C120 frequency (mhz) 0 2228 g06 51015 amplitude (db) 20 25 30 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100C110 C120 frequency (mhz) 0 2228 g07 51015 amplitude (db) 20 25 30 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100C110 C120 code 7000060000 50000 40000 30000 20000 10000 0 2043 61496 2044 2228 g08 2042 2123 count 1910 input frequency (mhz) 0 snr (dbfs) 70 71 200 2228 g09 6968 50 100 150 72 downloaded from: http:///
ltc2228/ltc2227/ltc2226 7 222876fb typical performance characteristics ltc2228: sfdr vs input frequency, C1db, 2v range, 65msps ltc2228: snr and sfdr vs clock duty cycle, 65msps ltc2228: snr vs input level, f in = 30mhz, 2v range, 65msps ltc2228: sfdr vs input level, f in = 30mhz, 2v range, 65msps ltc2228: i vdd vs sample rate, 5mhz sine wave input, C1db ltc2228: i ovdd vs sample rate, 5mhz sine wave input, C1db, ov dd = 1.8v ltc2228: snr and sfdr vs sample rate, 2v range,f in = 5mhz, C1db input frequency (mhz) 0 100 9590 85 80 75 70 65 150 2228 g10 50 100 200 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 110100 9080 70 60 80 2228 g11 20 40 60 100 snr sfdr clock duty cycle (%) 30 snr and sfdr (dbfs) 60 2228 g12 40 50 70 100 9590 85 80 75 70 65 35 45 55 65 sfdr: dcs on sfdr: dcs off snr: dcs on snr: dcs off input level (dbfs) C60 C50 snr (dbc and dbfs) C40 C20 C30 C10 0 2228 g13 8070 60 50 40 30 20 10 0 dbfs dbc input level (dbfs) C60 C50 C40 C20 C30 C10 0 sfdr (dbc and dbfs) 2228 g14 120110 100 9080 70 60 50 40 30 20 dbfs dbc 90dbc sfdrreference line sample rate (msps) 0 8075 70 65 60 55 50 60 2228 g15 20 40 80 50 10 30 70 i vdd (ma) 2v range 1v range sample rate (msps) i ovdd (ma) 2228 g16 65 4 3 2 1 0 0 20 40 50 10 30 60 70 80 downloaded from: http:///
ltc2228/ltc2227/ltc2226 8 222876fb typical performance characteristics ltc2227: typical inl, 2v range, 40msps ltc2227: typical dnl, 2v range, 40msps ltc2227: 8192 point fft, f in = 5mhz, C1db, 2v range, 40msps ltc2228: 8192 point fft, f in = 30mhz, C1db, 2v range, 40msps ltc2227: 8192 point 2-tone fft, f in = 21.6mhz and 23.6mhz, C1db, 2v range, 40msps ltc2227: grounded input histogram, 40msps ltc2227: snr vs input frequency, C1db, 2v range, 40msps ltc2227: 8192 point fft, f in = 70mhz, C1db, 2v range, 40msps ltc2227: 8192 point fft, f in = 140mhz, C1db, 2v range, 40msps code 0 inl error (lsb) 3072 2227 g01 1024 2048 4096 1.000.75 0.50 0.25 0 C0.25C0.50 C0.75 C1.00 code 0 dnl error (lsb) 3072 2227 g02 1024 2048 4096 1.000.75 0.50 0.25 0 C0.25C0.50 C0.75 C1.00 frequency (mhz) 0 amplitude (db) 2227 g03 51 01 52 0 0 1020 30 40 50 60 70 80 90 100110 120 frequency (mhz) 0 amplitude (db) 2227 g04 51 01 52 0 0 1020 30 40 50 60 70 80 90 100110 120 frequency (mhz) 0 amplitude (db) 2227 g05 51 01 52 0 0 1020 30 40 50 60 70 80 90 100110 120 frequency (mhz) 0 amplitude (db) 2227 g06 51 01 52 0 0 1020 30 40 50 60 70 80 90 100110 120 frequency (mhz) 0 amplitude (db) 2227 g07 51 01 52 0 0 1020 30 40 50 60 70 80 90 100110 120 code 2050 count 2227 g08 2051 2052 7000060000 50000 40000 30000 20000 10000 0 1424 61538 2558 input frequency (mhz) 0 snr (dbfs) 70 71 200 2227 g09 6968 50 100 150 72 downloaded from: http:///
ltc2228/ltc2227/ltc2226 9 222876fb typical performance characteristics ltc2227: sfdr vs input frequency, C1db, 2v range, 40msps ltc2227: sfdr vs input level, f in = 5mhz, 2v range, 40msps ltc2227: i vdd vs sample rate, 5mhz sine wave input, C1db ltc2227: snr and sfdr vs sample rate, 2v range,f in = 5mhz, C1db input frequency (mhz) 0 100 9590 85 80 75 70 65 150 2227 g10 50 100 200 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 110100 9080 70 60 2227 g11 40 20 60 80 snr sfdr ltc2227: snr vs input level, f in = 5mhz, 2v range, 40msps input level (dbfs) C60 C50 snr (dbc and dbfs) C40 C20 C30 C10 0 2227 g12 8070 60 50 40 30 20 10 0 dbfs dbc 2227 g13 input level (dbfs) C60 C50 C40 C20 C30 C10 0 snr (dbc and dbfs) 120110 100 9080 70 60 50 40 30 20 dbfs dbc 90dbc sfdrreference line 2227 g14 sample rate (msps) 0 5045 40 35 30 20 40 50 10 30 i vdd (ma) 2v range 1v range ltc2227: i ovdd vs sample rate, 5mhz sine wave input, C1db, ov dd = 1.8v 2227 g15 sample rate (msps) i ovdd (ma) 43 2 1 0 0 20 40 50 10 30 downloaded from: http:///
ltc2228/ltc2227/ltc2226 10 222876fb typical performance characteristics ltc2226: typical inl, 2v range, 25msps ltc2226: typical dnl, 2v range, 25msps ltc2226: 8192 point fft, f in = 5mhz, C1db, 2v range, 25msps ltc2226: 8192 point fft, f in = 30mhz, C1db, 2v range, 25msps ltc2226: 8192 point 2-tone fft, f in = 10.9mhz and 13.8mhz, C1db, 2v range, 25msps ltc2226: grounded input histogram, 25msps ltc2226: snr vs input frequency, C1db, 2v range, 25msps ltc2226: 8192 point fft, f in = 70mhz, C1db, 2v range, 25msps ltc2226: 8192 point fft, f in = 140mhz, C1db, 2v range, 25msps code 0 inl error (lsb) 3072 2226 g01 1024 2048 4096 1.000.75 0.50 0.25 0 C0.25C0.50 C0.75 C1.00 code 0 dnl error (lsb) 3072 2226 g02 1024 2048 4096 1.000.75 0.50 0.25 0 C0.25C0.50 C0.75 C1.00 frequency (mhz) 0 amplitude (db) 2226 g03 24 681 0 12 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100C110 C120 frequency (mhz) 0 amplitude (db) 2226 g04 24 681 0 12 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100C110 C120 frequency (mhz) 0 amplitude (db) 2226 g05 24 681 0 12 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100C110 C120 frequency (mhz) 0 amplitude (db) 2226 g06 24 681 0 12 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100C110 C120 frequency (mhz) 0 amplitude (db) 2226 g07 24 681 0 12 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100C110 C120 code count 2050 2226 g08 2048 2049 7000060000 50000 40000 30000 20000 10000 0 61758 1607 2155 input frequency (mhz) 0 snr (dbfs) 70 71 200 2226 g09 6968 50 100 150 72 downloaded from: http:///
ltc2228/ltc2227/ltc2226 11 222876fb typical performance characteristics ltc2226: sfdr vs input frequency, C1db, 2v range, 25msps ltc2226: sfdr vs input level, f in = 5mhz, 2v range, 25msps ltc2226: i vdd vs sample rate, 5mhz sine wave input, C1db ltc2226: snr and sfdr vs sample rate, 2v range,f in = 5mhz, C1db ltc2226: snr vs input level, f in = 5mhz, 2v range, 25msps ltc2226: i ovdd vs sample rate, 5mhz sine wave input, C1db, ov dd = 1.8v input frequency (mhz) 0 100 9590 85 80 75 70 65 150 2226 g10 50 100 200 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 110100 9080 70 60 40 50 2226 g11 10 20 30 snr sfdr input level (dbfs) C60 C50 snr (dbc and dbfs) C40 C20 C30 C10 0 2227 g12 8070 60 50 40 30 20 10 0 dbfs dbc input level (dbfs) C60 C50 C40 C20 C30 C10 0 sfdr (dbc and dbfs) 2226 g13 120110 100 9080 70 60 50 40 30 20 dbfs dbc 90dbc sfdrreference line sample rate (msps) 0 3530 25 20 15 30 2226 g14 10 20 25 51 5 3 5 i vdd (ma) 2v range 1v range sample rate (msps) i ovdd (ma) 2226 g15 32 1 0 0 20 30 51 5 35 10 25 downloaded from: http:///
ltc2228/ltc2227/ltc2226 12 222876fb pin functions a in + (pin 1): positive differential analog input. a in C (pin 2): negative differential analog input. refh (pins 3, 4): adc high reference. short together and bypass to pins 5, 6 with a 0.1f ceramic chip capacitor as close to the pin as possible. also bypass to pins 5, 6 with an additional 2.2f ceramic chip capacitor and to ground with a 1f ceramic chip capacitor. refl (pins 5, 6): adc low reference. short together and bypass to pins 3, 4 with a 0.1f ceramic chip capacitor as close to the pin as possible. also bypass to pins 3, 4 with an additional 2.2f ceramic chip capacitor and to ground with a 1f ceramic chip capacitor. v dd (pins 7, 32): 3v supply. bypass to gnd with 0.1f ceramic chip capacitors.gnd (pin 8): adc power ground. clk (pin 9): clock input. the input sample starts on the positive edge.shdn (pin 10): shutdown mode selection pin. connecting shdn to gnd and oe to gnd results in normal operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance.oe (pin 11): output enable pin. refer to shdn pin function. nc (pins 12, 13): do not connect these pins. d0-d11 (pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): digital outputs. d11 is the msb. ognd (pin 20): output driver ground. ov dd (pin 21): positive supply for the output drivers. bypass to ground with 0.1f ceramic chip capacitor. of (pin 28): over/under flow output. high when an over or under ? ow has occurred. mode (pin 29): output format and clock duty cycle stabilizer selection pin. connecting mode to gnd selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. v dd selects 2s complement output format and turns the clock duty cycle stabilizer off.sense (pin 30): reference programming pin. connecting sense to v cm selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. v cm (pin 31): 1.5v output and input common mode bias. bypass to ground with 2.2f ceramic chip capacitor. exposed pad (pin 33): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. downloaded from: http:///
ltc2228/ltc2227/ltc2226 13 222876fb functional block diagram diff ref amp ref buf 2.2f 1f 1f 0.1f internal clock signals refh refl clock/duty cycle control range select 1.5v reference first pipelined adc stage fifth pipelined adc stage sixth pipelined adc stage fourth pipelined adc stage second pipelined adc stage refh refl clk shift register and correction oe m0de ognd ov dd 222876 f01 input s/h sense v cm a in C a in + 2.2f third pipelined adc stage output drivers control logic shdn of d11d0 ?? ? figure 1. functional block diagram downloaded from: http:///
ltc2228/ltc2227/ltc2226 14 222876fb timing diagram t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t l n C 4 n C 3 n C 2 n C 1 clk d0-d11, of 222876 td01 n C 5 n timing diagram downloaded from: http:///
ltc2228/ltc2227/ltc2226 15 222876fb applications information dynamic performancesignal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamen- tal input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the ? rst ? ve harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log ((v2 2 + v3 2 + v4 2 + . . . vn 2 )/v1) where v1 is the rms amplitude of the fundamental fre-quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the ? fth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are ap-plied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa C fb and 2fb C fa. the intermodula- tion distortion is de? ned as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spuri- ous noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. aperture delay time the time from when clk reaches mid-supply to the in- stant that the input signal is held by the sample-and-hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) downloaded from: http:///
ltc2228/ltc2227/ltc2226 16 222876fb applications information converter operation as shown in figure 1, the ltc2228/ltc2227/ltc2226 is a cmos pipelined multi-step converter. the converter has six pipelined adc stages; a sampled analog input will result in a digitized value ? ve cycles later (see the timing diagram section). for optimal ac performance the analog inputs should be driven differentially. for cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. the clk input is single-ended. the ltc2228/ltc2227/ltc2226 has two phases of operation, determined by the state of the clk input pin. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue ampli? er. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is ampli? ed and output by the residue ampli? er. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h dur- ing this high phase of clk. when clk goes back low, the ? rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third, fourth and ? fth stages, resulting in a ? fth stage residue that is sent to the sixth stage adc for ? nal evaluation. each adc stage following the ? rst has additional range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2228/ ltc2227/ltc2226 cmos differential sample-and-hold. the analog inputs are connected to the sampling capaci- tors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summa- tion of all other capacitance associated with each input. during the sample phase when clk is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. when clk transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. v dd v dd v dd 1515 c parasitic 1pfc parasitic 1pf c sample 4pf c sample 4pf ltc2228/27/26 a in + a in C clk 222876 f02 figure 2. equivalent input circuit downloaded from: http:///
ltc2228/ltc2227/ltc2226 17 222876fb applications information single-ended inputfor cost-sensitive applications, the analog inputs can be driven single ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in C should be connected to 1.5v or v cm . common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.5v. the v cm output pin (pin 31) may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2f or greater capacitor. input drive impedance as with all high performance, high speed adcs, the dy- namic performance of the ltc2228/ltc2227/ltc2226 can be in? uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can in? uence sfdr. at the falling edge of clk, the sample-and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sam- pling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2228/ltc2227/ltc2226 being driven by an rf transformer with a center tapped sec- ondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 for each adc input. a disadvantage of us- ing a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. figure 4 demonstrates the use of a differential ampli? er to convert a single-ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the sfdr at high input frequencies. 2525 25 25 0.1f a in + a in C 12pf 2.2f v cm ltc2228/27/26 analog input 0.1f t1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 222876 f03 figure 3. single-ended to differential conversion using a transformer downloaded from: http:///
ltc2228/ltc2227/ltc2226 18 222876fb applications information figure 5 shows a single-ended input circuit. the impedance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. the 25 resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. 25 25 12pf 2.2f v cm ltc2228/27/26 222876 f04 C C + + cm analog input high speed differential amplifier a in + a in C figure 4. differential drive with an ampli? er 25 0.1f analog input v cm a in + a in C 1k 12pf 222876 f05 2.2f 1k 25 0.1f ltc2228/27/26 figure 5. single-ended drive for input frequencies above 70mhz, the input circuits of figure 6, 7 and 8 are recommended. the balun transformer gives better high frequency response than a ? ux coupled center tapped transformer. the coupling capacitors allow the analog inputs to be dc biased at 1.5v. in figure 8, the series inductors are impedance matching elements that maximize the adc bandwidth. 2525 12 12 0.1f a in + a in C 8pf 2.2f v cm ltc2228/27/26 analog input 0.1f 0.1f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 222876 f06 figure 6. recommended front-end circuit for input frequencies between 70mhz and 170mhz 2525 0.1f a in + a in C 2.2f v cm ltc2228/27/26 analog input 0.1f 0.1f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 222876 f07 figure 7. recommended front-end circuit for input frequencies between 170mhz and 300mhz 2525 0.1f a in + a in C 2.2f v cm ltc2228/27/26 analog input 0.1f 0.1f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors, inductors are 0402 package size 222876 f08 6.8nh 6.8nh figure 8. recommended front-end circuit for input frequencies above 300mhz downloaded from: http:///
ltc2228/ltc2227/ltc2226 19 222876fb typical applications reference operation figure 9 shows the ltc2228/ltc2227/ltc2226 refer- ence circuitry consisting of a 1.5v bandgap reference, a difference ampli? er and switching and control circuit. the internal voltage reference can be con? gured for two pin selectable input ranges of 2v (1v differential) or 1v (0.5v differential). tying the sense pin to v dd selects the 2v range; tying the sense pin to v cm selects the 1v range. the 1.5v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference ampli? er to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.5v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. the difference ampli? er generates the high and low reference for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins. the multiple output pins are needed to reduce package inductance. bypass capacitors must be connected as shown in figure 9. other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by ap- plying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1f ceramic capacitor. v cm refh sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ? v sense for 0.5v < v sense < 1v 1.5v refl 2.2f 2.2f internal adchigh reference buffer 0.1f 222876 f09 ltc2228/27/26 4 diff amp 1f 1f internal adclow reference 1.5v bandgap reference 1v 0.5v range detect and control figure 9. equivalent reference circuit v cm sense 1.5v 0.75v 2.2f 12k 1f 12k 222876 f10 ltc2228/27/26 figure 10. 1.5v range adc downloaded from: http:///
ltc2228/ltc2227/ltc2226 20 222876fb input rangethe input range can be set based on the application. the 2v input range will provide the best signal-to-noise performance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 3.8db. see the typical performance characteristics section. driving the clock input the clk input can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low jitter squaring circuit before the clk pin (figure 11). the noise performance of the ltc2228/ltc2227/ltc2226 can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, such as when digi- tizing high input frequencies, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, ? lter the clk signal to reduce wideband noise and distortion products generated by the source. figures 12 and 13 show alternatives for converting a differential clock to the single-ended clk input. the use of a transformer provides no incremental contribution to phase noise. the lvds or pecl to cmos translators provide little degradation below 70mhz, but at 140mhz will degrade the snr compared to the transformer solution. the nature of the received signals also has a large bear- ing on how much snr degradation will be experienced. for high crest factor signals such as wcdma or ofdm, where the nominal power level must be at least 6db to 8db below full scale, the use of these translators will have a lesser impact. the transformer in the example may be terminated with the appropriate termination for the signaling in use. the use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. the center tap may be bypassed to ground through a capacitor close to the adc if the differential signals originate on a different plane. the use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10 to 20 series resistor to act as both a lowpass ? lter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for re? ections. applications information clk 1k1k ferrite bead clean supply 222876 f11 ltc2228/ ltc2227/ ltc2226 0.1f 0.1f sinusoidal clock input 4.7f nc7svu04 50 figure 11. single-ended clk drive clk 100 0.1f 4.7f ferrite bead clean supply if lvds use fin1002 or fin1018. for pecl, use az1000elt21 or similar 223876 f12 ltc2238/ ltc2237/ ltc2236 clk 5pf-30pf etc1-1t 0.1f v cm ferrite bead differential clock input 223876 f13 ltc2238/ ltc2237/ ltc2236 figure 13. lvds or pecl clk drive using a transformer figure 12. clk drive using an lvds or pecl-to-cmos converter downloaded from: http:///
ltc2228/ltc2227/ltc2226 21 222876fb applications information maximum and minimum conversion rates the maximum conversion rate for the ltc2228/ltc2227/ ltc2226 is 65msps (ltc2228), 40msps (ltc2227), and 25msps (ltc2226). for the adc to operate properly, the clk signal should have a 50% (5%) duty cycle. each half cycle must have at least 7.3ns (ltc2228), 11.8ns (ltc2227), and 18.9ns (ltc2226) for the adc internal cir- cuitry to have enough settling time for proper operation. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. the lower limit of the ltc2228/ltc2227/ltc2226 sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small-valued capacitors. junction leak- age will discharge the capacitors. the speci? ed minimum operating frequency for the ltc2228/ltc2227/ltc2226 is 1msps. ltc2228/27/26 222876 f14 ov dd v dd v dd 0.1f 43 typical data output ognd ov dd 0.5vto 3.6v predriver logic data from latch oe figure 14. digital output buffer digital outputs table 1 shows the relationship between the analog input voltage, the digital data bits and the over? ow bit. table 1. output codes vs input voltage a in + C a in C (2v range) of d11-d0 (offset binary) d11-d0 (2s complement) >+1.000000v +0.999512v +0.999024v 10 0 1111 1111 11111111 1111 1111 1111 1111 1110 0111 1111 11110111 1111 1111 0111 1111 1110 +0.000488v 0.000000v C0.000488v C0.000976v 00 0 0 1000 0000 00011000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 00010000 0000 0000 1111 1111 1111 1111 1111 1110 C0.999512v C1.000000v ltc2228/ltc2227/ltc2226 22 222876fb applications information digital outputs of the ltc2228/ltc2227/ltc2226 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs.data format using the mode pin, the ltc2228/ltc2227/ltc2226 parallel digital output can be selected for offset binary or 2s complement format. connecting mode to gnd or 1/3v dd selects offset binary output format. connecting mode to 2/3v dd or v dd selects 2s complement output format. an external resistor divider can be used to set the 1/3v dd or 2/3v dd logic values. table 2 shows the logic states for the mode pin. table 2. mode pin function mode pin output format clock duty cycle stabilizer 0 offset binary off 1/3v dd offset binary on 2/3v dd 2s complement on v dd 2s complement off over? ow bit when of outputs a logic high the converter is either over- ranged or underranged. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to 3.6v. ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . output enablethe outputs may be disabled with the output enable pin, oe . oe high disables all data outputs including of. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. the output hi-z state is intended for use during long periods of inactivity. sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dis- sipates 15mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. grounding and bypassing the ltc2228/ltc2227/ltc2226 require a printed circuit board with a clean, unbroken ground plane. a multilayer board with an internal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refh, and refl pins. bypass capaci- tors must be located as close to the pins as possible. of particular importance is the 0.1f capacitor between refh and refl. this capacitor should be placed as close to the device as possible (1.5mm or less). a size 0402 ceramic capacitor is recommended. the large 2.2f capacitor be- tween refh and refl can be somewhat further away. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. downloaded from: http:///
ltc2228/ltc2227/ltc2226 23 222876fb typical applications the ltc2228/ltc2227/ltc2226 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2228/ltc2227/ ltc2226 is transferred from the die through the bottom- side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of suf? cient area. clock sources for undersampling undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. a clock source that degrades snr of a full-scale signal by 1db at 70mhz will degrade snr by 3db at 140mhz, and 4.5db at 190mhz. in cases where absolute clock frequency accuracy is relatively unimportant and only a single adc is required, a 3v canned oscillator from vendors such as saronix or vectron can be placed close to the adc and simply connected directly to the adc. if there is any distance to the adc, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. you must not allow the clock to overshoot the supplies or performance will suffer. do not ? lter the clock signal with a narrow band ? lter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. the lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a ? lter close to the adc may be bene? cial. this ? lter should be close to the adc to both reduce roundtrip re? ection times, as well as reduce the susceptibility of the traces between the ? lter and the adc. if you are sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. if your clock is also used to drive digital devices such as an fpga, you should locate the oscillator, and any clock fan-out devices close to the adc, and give the routing to the adc precedence. the clock signals to the fpga should have series termination at the source to prevent high frequency noise from the fpga disturbing the substrate of the clock fan-out device. if you use an fpga as a programmable divider, you must re-time the signal using the original oscillator, and the re- timing ? ip-? op as well as the oscillator should be close to the adc, and powered with a very quiet supply. for cases where there are multiple adcs, or where the clock source originates some distance away, differential clock distribution is advisable. this is advisable both from the perspective of emi, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer pcbs. the differential pairs must be close together, and distanced from other signals. the differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart. downloaded from: http:///
ltc2228/ltc2227/ltc2226 24 222876fb applications information 12 c8 0.1f c11 0.1f 34 5 v dd 7 v dd v dd gnd 9 32 v cm 31 30 29 33 jp2 oe 10 11 8 c72.2f c6 1f c9 1f c4 0.1f c212pf v dd v dd v dd gnd jp1 shdn c152.2f c16 0.1f c18 0.1f c254.7f e2v dd 3ve4 pwr gnd v dd v cc 222876 ta02 c17 0.1f c20 0.1f c19 0.1f c14 0.1f r1033 e1 ext ref r141k r151k r161k r71k r849.9 r324.9 r2 24.9 r6 24.9 r1 opt r424.9 r5 50 t1 etc1-1t c1 0.1f c3 0.1f j3 clock input nc7svu04 nc7svu04 c13 0.1f c10 0.1f c5 4.7f 6.3v l1 bead v dd c12 0.1f r91k j1 analog input a in + a in C refhrefh 6 refl reflv dd clkshdn v dd v cm sensemode gnd ltc2228/ltc2227/ ltc2226 oe d11 gnd d0 nc nc d1d2 d3 d5 d4d6 d8 d9 of ov dd v cc ognd d10 d7 26 25 1213 14 15 17 1618 22 23 27 28 21 20 24 19 oe1i 0 oe2 le1 le2 v cc v cc v cc gnd gnd gndi 1 i 2 i 4 i 3 i 5 i 7 i 8 i 12 i 11 i 10 i 13 i 14 i 15 i 9 o11 o10 i 6 v cc o0 gndgnd gnd v cc v cc gnd 3445 39 42 25 48 24 1 4746 44 43 41 40 38 37 36 35 33 32 30 29 27 26 v cc 28 74vcx16373mtd 3121 15 18 10 4 7 r n1c 33 23 5 6 8 9 11 12 13 14 16 17 19 20 22 23 gnd o1o2 o4 o3o5 o7 o8 o12o13 o14 o15 o9 o6 2523 27 29 31 33 35 37 3921 19 15 1713 9 7 1 3 5 2 4 11 2624 3028 3432 38 40 3937 35 33 31 29 27 25 23 21 19 17 15 13 11 97 5 3 1 40 3201s-40g1 3836 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 36 a3 a2 a1 a0 sda wp v cc 12 3 4 8 24lc025 76 5 scl 2220 16 1814 10 86 12 12 3 5 ?? 4 v cm 12 v dd v dd 34 2/3v dd 56 1/3v dd 78 gnd jp4 mode 12 v dd 34 v cm v dd v cm 56 ext ref jp3 sense r n1b 33 r n1a 33 r n2d 33 r n2c 33 r n2b 33 r n2a 33 r n3d 33 r n3c 33 r n3b 33 r n3a 33 r n4d 33 r n4b 33 r n4a 33 r1310k r1110k r1210k r n4c 33 r n1d 33 c28 1f c27 0.01f v cc v dd nc7sv86p5x byp gnd adj out shdn gnd in 12 3 4 8 lt1763 76 5 gnd r18100k r17105k c26 10f 6.3v e3 gnd c21 0.1f c22 0.1f c23 0.1f c24 0.1f downloaded from: http:///
ltc2228/ltc2227/ltc2226 25 222876fb applications information silkscreen top topside inner layer 2 gnd downloaded from: http:///
ltc2228/ltc2227/ltc2226 26 222876fb applications information inner layer 3 power bottomside silkscreen bottom downloaded from: http:///
ltc2228/ltc2227/ltc2226 27 222876fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 5.00 p 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 p 0.10 31 12 32 bottom viewexposed pad 3.50 ref (4-sides) 3.45 p 0.10 3.45 p 0.10 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 C 0.05 0.70 p 0.05 3.50 ref (4 sides) 4.10 p 0.05 5.50 p 0.05 0.25 p 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer r = 0.05 typ 3.45 p 0.05 3.45 p 0.05 downloaded from: http:///
ltc2228/ltc2227/ltc2226 28 222876fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0608 rev b printed in usa related parts part number description comments ltc1748 14-bit, 80msps, 5v adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr lt1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain lt1994 low noise, low distortion fully differential input/output ampli? er/driver low distortion: C94dbc at 1mhz ltc2202 16-bit, 10msps, 3v adc, lowest power 150mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3v adc, lvds outputs 1250mw, 78db snr, 100db sfdr, 64-pin qfn ltc2220-1 12-bit, 185msps, 3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2225 12-bit, 10msps, 3v adc, lowest power 60mw, 71.3db snr, 90db sfdr, 32-pin qfn ltc2226 12-bit, 25msps, 3v adc, lowest power 75mw, 71.4db snr, 90db sfdr, 32-pin qfn ltc2227 12-bit, 40msps, 3v adc, lowest power 120mw, 71.4db snr, 90db sfdr, 32-pin qfn ltc2228 12-bit, 65msps, 3v adc, lowest power 205mw, 71.3db snr, 90db sfdr, 32-pin qfn ltc2229 12-bit, 80msps, 3v adc, lowest power 211mw, 70.6db snr, 90db sfdr, 32-pin qfn ltc2236 10-bit, 25msps, 3v adc, lowest power 75mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2237 10-bit, 40msps, 3v adc, lowest power 120mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2238 10-bit, 65msps, 3v adc, lowest power 205mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2239 10-bit, 80msps, 3v adc, lowest power 211mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2245 14-bit, 10msps, 3v adc, lowest power 60mw, 74.4db snr, 90db sfdr, 32-pin qfn ltc2246 14-bit, 25msps, 3v adc, lowest power 75mw, 74.5db snr, 90db sfdr, 32-pin qfn ltc2247 14-bit, 40msps, 3v adc, lowest power 120mw, 74.4db snr, 90db sfdr, 32-pin qfn ltc2248 14-bit, 65msps, 3v adc, lowest power 205mw, 74.3db snr, 90db sfdr, 32-pin qfn ltc2249 14-bit, 80msps, 3v adc, lowest power 222mw, 73db snr, 90db sfdr, 32-pin qfn ltc2250 10-bit, 105msps, 3v adc, lowest power 320mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2251 10-bit, 125msps, 3v adc, lowest power 395mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2252 12-bit, 105msps, 3v adc, lowest power 320mw, 70.2db snr, 88db sfdr, 32-pin qfn ltc2253 12-bit, 125msps, 3v adc, lowest power 395mw, 70.2db snr, 88db sfdr, 32-pin qfn ltc2254 14-bit, 105msps, 3v adc, lowest power 320mw, 72.4db snr, 88db sfdr, 32-pin qfn ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if ampli? er/adc driver with digitally controlled gain 450mhz to 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion high iip3: 20dbm at 1.9ghz, quadrature demodulator integrated lo quadrature generator lt5516 800mhz to 1.5ghz direct conversion high iip3: 21.5dbm at 900mhz, quadrature demodulator integrated lo quadrature generator lt5517 40mhz to 900mhz direct conversion high iip3: 21dbm at 800mhz, quadrature demodulator integrated lo quadrature generator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz. nf = 12.5db, 50w single-ended rf and lo ports downloaded from: http:///

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